GateRL: Automated Circuit Design Framework of CMOS Logic Gates Using Reinforcement Learning

This paper proposes a GateRL that is an automated circuit design framework of CMOS logic gates based on reinforcement learning. Because there are constraints in the connection elements, action masking scheme employed. It also reduces size space leading to improvement learning speed. The consists agent for and environment state, mask, reward. State reward generated from matrix describes current configuration, mask obtained matrix. given rise by deep Q-network 4 fully connected network layers agent. In particular, separate replay buffers devised success transitions failure expedite training process. proposed trained with 2 inputs, 1 output, NMOS transistors, PMOS transistors all target gates, such as buffer, inverter, AND, OR, NAND, NOR. Consequently, outputs one-transistor two-transistor three-transistor operations these resultant logics verified SPICE simulation.